Keywords

ddr ram

memory


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1. DDR2 667MHz, PC6400


2. 240-pin socket type dual in line memory module (DIMM)
3. 2.6V power supply
4. Data rate: 667Mbps (max.)
5. 2.5 V (SSTL-2 compatible) I/O
6. Double data rate architecture, two data transfers per clock
7. Bi-directional, data strobe (DQS) is transmitted/received with data, to be used in capturing data at the receiver
8. Data inputs and outputs are synchronized with DQS
9. DQS is edge aligned with data for read, center aligned with data for write
10. Differential clock inputs (CK and CK)
11. DLL aligns DQ and DQS transitions with CK transitions
12. Commands entered on each positive CK edge, data referenced to both edges of DQS
13. Auto precharge option for each burst access
14. Programmable burst length: 2, 4, 8
15. Programmable/CAS latency (CL): 3
16. Programmable output driver strength: normal/weak
17. Refresh cycles: (8192 refresh cycles/64ms)
18. 7.8US maximum average periodic refresh interval
19. 2 variations of refresh
20. Auto refresh
21. Self refresh



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Posted by Sunny Lee
e-MailContact company
Company
Shenzhen Mainbert Technology Co., Ltd
Address Room 3102, 31/F, Nanguangjiejia Bldg, Shen
City & ZIP
518000
Country
China
Phone
For registered Members only.
Fax
For registered Members only.
Key Customers / Clientele
Company Profile Shenzhen Mainbert Technology Co., Ltd. is a professional manufacturer and trader for PC products. Our main series include DDR ram, MP4, MP3 and SD card, MMC card, GSM mobile and USB flash memory disk. We now intend to find agents for these items around the world.
URLFor registered Members only.
Rating (0 reviews)
Popular tags
Keywords (seperated by comma)ddr ram .memory
Product Specifications1. DDR2 667MHz, PC6400

2. 240-pin socket type dual in line memory module (DIMM)
3. 2.6V power supply
4. Data rate: 667Mbps (max.)
5. 2.5 V (SSTL-2 compatible) I/O
6. Double data rate architecture, two data transfers per clock
7. Bi-directional, data strobe (DQS) is transmitted/received with data, to be used in capturing data at the receiver
8. Data inputs and outputs are synchronized with DQS
9. DQS is edge aligned with data for read, center aligned with data for write
10. Differential clock inputs (CK and CK)
11. DLL aligns DQ and DQS transitions with CK transitions
12. Commands entered on each positive CK edge, data referenced to both edges of DQS
13. Auto precharge option for each burst access
14. Programmable burst length: 2, 4, 8
15. Programmable/CAS latency (CL): 3
16. Programmable output driver strength: normal/weak
17. Refresh cycles: (8192 refresh cycles/64ms)
18. 7.8US maximum average periodic refresh interval
19. 2 variations of refresh
20. Auto refresh
21. Self refresh
Industry Categorycomputer
Quality/Safety Certifications
Delivery Lead Time3`5day
Payment & Price TermsT/T
My Offersddr 400
ddr2 667
ddr2 800
Product Portfolio / Other Products
Customersworldwide
Detailed Company Introduction
FOB Price & Port500billion usd
Packaging Detailsmore than 500
Our Team50
Web SiteFor registered Members only.

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Product Details
Product id 216949
Visits  317
Date 2008.09.19
 

Execution time:0.083732128143311